1. Field of the Invention
The present invention relates to a method of fabricating semiconductor devices, and more particularly to forming self-aligned contacts and local interconnects of semiconductor devices.
2. Description of the Related Art
In recent years, the size of integrated circuit devices continues to decrease resulting in considerable increase of the packing densities for these devices. The performance of the integrated circuit devices also improves as a result while the manufacture costs have gone down as well.
However, the performance of denser integrated circuit devices could drop when smaller process parameters are used. Accordingly, the issue of maintaining or controlling the precision of contact windows is particularly important as the density of integrated circuit devices continues to increase for future generations of these devices. This etching control issue is even more critical for integrated circuit devices with multiple polysilicon layers. Therefore, a so-called self-aligned contact (SAC) process which can reduce contact area is developed to deal with this issue.
Various SAC processes exist today. For example, U.S. Pat. No. 6,271,081 to Kinoshita et al. (the entire disclosure of which is herein incorporated by reference) provides a method of forming self-aligned contacts and local interconnects using self-aligned local interconnects. Referring now more particularly to FIGS. 1A-1D, there are illustrated the cross sectional views of the SAC process disclosed by Kinoshita et al. The figures show a portion of the core region 104 and also a portion of the peripheral region 106 in which an IC device such as a flash memory is built. FIG. 1A shows a portion of a partially completed dual gate flash memory device after a dielectric layer is deposited according to the prior art. The multi-layer stacked gate structure 110 of the core region 104 is formed on a semiconductor substrate 102. The multi-layer stacked gate structure 110 comprises a gate dielectric layer 112 of a material such as an oxide or nitride, a floating gate layer 114, an interpoly dielectric layer 116, a control gate layer 118, a gate silicide layer 120, and a cap dielectric layer 122. In the peripheral region 106, the multi-layer stacked gate structure only comprises a gate dielectric layer 112, a polysilicon gate layer 118, a gate silicide layer 120, and a cap dielectric layer 122. Sidewall spacers 130 and a liner layer 131 are formed on the sidewalls of the multi-layer stacked gate structure to protect the structure from over etching and short circuit. A common source 142 is formed between two multi-layer stacked gate structures and drains 144 are also formed in the semiconductor substrate 102 and spaced apart from the common source by channel regions 146. In order to decrease the contact resistance and thus to increase the operational speed of the IC device, source/drain suicides 129 are formed. Thereafter, a dielectric layer 132 is formed over the entire semiconductor substrate surface.
FIG. 1B shows the simultaneously forming of the source/drain contact 162 and interconnect contact opening 163 by using a photoresist pattern 166 as a mask. Then, FIG. 1C shows the reopening of the interconnect contact 165 alone by using a second photoresist pattern 168 as a mask to remove a portion of the cap dielectric layer 122 and expose the polysilicon gate layer 118 in the peripheral region 106. After the removal of the second photoresist mask, FIG. 1D shows a metal layer being deposited and planarized to complete the formation of both the SAC contact 170 and the interconnect contact 171.
From the above description, one of ordinary skills in the art can readily see that a lot of photolithography and etching steps are needed to complete the formation of both the SAC contact and the interconnect contact for a semiconductor device. These additional steps significantly increase the complexity and cost for mass-production.
Another SAC process has been proposed to address this issue by opening both the SAC contact and the interconnect contact at the same time. For example, U.S. Pat. No. 5,668,065 to Chen-Hsi Lin (the entire disclosure of which is herein incorporated by reference) provides a method of simultaneously forming silicide-based self-aligned contacts and local interconnects. Referring now more particularly to FIGS. 2A-2C, there are illustrated the cross sectional views of the SAC process disclosed by Lin. The figures show a portion of the core region and also a portion of the peripheral region in which a MOSFET IC device is built. FIG. 2A shows a first photoresist pattern 244 formed to define source/drain contacts and interconnect contacts. The gates 220 of the IC device are formed on a semiconductor substrate 210. The gate structure comprises a gate dielectric layer 222, a polysilicon gate layer 224, a tungsten silicide layer 226, and a cap dielectric layer 228. Sidewall spacers 230 and a liner layer 232 such as a thin oxide layer are formed on the sidewalls of the gate structure to protect the structure from over etching and short circuit. A common source 214 is formed between two gate structures, and drains 212 are also formed in the semiconductor substrate and spaced apart from the common source by channel regions. The liner layer 232 is also formed over a field oxide isolation region 216. Thereafter, the source/drain SAC contact opening and interconnect contact opening are simultaneously formed using a photoresist pattern 234 as a mask.
FIG. 2B shows a cross-sectional view of the IC substrate in which an amorphous silicon layer 240 is formed and etched by using a second photoresist pattern 244 as a mask to remove the exposed portion of the amorphous layer and liner layer. After the second photoresist pattern is removed, FIG. 2C shows the forming of a silicide layer 250 in both the source/drain SAC contact 252 and the interconnect contact.
However, this approach can not be used in a high speed operation device if interlayer dielectric (ILD) thickness difference occurs between the core region and the peripheral region as described in FIG. 1D. Therefore, there is still a need for a process which can effectively solve the above-mentioned problems of the prior art.